1. Technical Field
The present application relates generally to an improved system and method for performing static analysis of integrated circuit designs. More specifically, the present application is directed to a system and method for driving values to so-called “don't care” (DC) adjusted/untimed nets, or net segments, of an integrated circuit design to thereby identify timing problems.
2. Description of Related Art
In the field of integrated circuit (IC) design, digital electronic circuits are typically initially represented by a high-level abstraction written in a hardware description language (HDL). The HDL representation allows a circuit designer to express all the desired functionality of a digital electronic circuit at the register transfer level (RTL) of abstraction. The HDL representation is then converted into a circuit file through a process known as synthesis that involves translation and optimization. Finally, static timing analysis and formal verification, e.g., functional analysis, are performed on the circuit file. Static timing analysis verifies that the circuit design performs at target clock speeds. Formal verification ensures that the circuit file is functionally correct compared to the HDL. It should be noted that non-formal methods of verification may also be utilized.
Essentially, static timing analysis is used to verify that transitioning values from source latches to sink latches in the nets of the circuit design will satisfy the timing requirements of the synchronous logic. In order to simplify static timing analysis, circuit designers commonly identify and eliminate a selected set of non-critical timing paths throughout a circuit design when performing static timing analysis on the circuit design. Such set of non-critical timing paths are usually referred to as a snip, exception, or “don't care” (DC) adjusted list or file (referred to hereafter as a DC adjusted (dcadj) list). The dcadj list enables the prevention of propagation of arrival times and required arrival times through pins, the changing of delays through pins, and the changing of the phases of arrival times propagating through pins, and other modifications of static timing constraints during static analysis. The dcadj list may be passed to the static timing tools to thereby identify to the static timing tools that certain nets, or net segments, need not adhere to static timing requirements since their value will not transition or change.
For most circuit designs, the practice of using dcadj lists is usually done to eliminate false timing violations during static timing analysis. That is, certain nets or net segments may be eliminated from static timing analysis because they do not need to adhere to timing requirements because their values are at a steady state. For example, signals which determine the mode of operation for some logic will only change during initialization. During normal operation, those signals are expected to never change. Hence they do not need to meet timing requirements.
A problem arises, however, in that a human designer decides on the dcadj list that is provided to the static timing tool. Thus, this designer may think the dcadj list is correct, however, they may fail to realize that some entries in the dcadj list will not be “don't care” in certain modes of operation and should be removed from the dcadj list. It is also possible that the entry is in a form of a regular expression which inadvertently matches more points (nets or box/pin pairs) in the logic than intended.
As a result, when the critical timing paths of some circuit designs are masked as part of the cone of logic of the eliminated non-critical timing paths, i.e. the DC adjusted nets, the elimination of the non-critical timing paths may lead to a real timing violation not being detected during static timing analysis. For example, glitches in these DC adjusted (dcadj) nets may be missed if their source latches transition in value. This may be true even if the source latch transitions eventually result in the dcadj net holding its value. Such real timing violations may not even be realized until actual hardware is manufactured.